The present invention relates to a digital computer, and in particular, to a data processing system in which a succeeding instruction is concurrently executed with a preceding instruction before a preceding instruction conceptually ahead thereof completes its execution, using a predicted result of the preceding instruction, thereby achieving a higher-speed processing.
In a general-purpose, large-sized digital computer, simultaneous processing of a plurality of instructions has been generally effected, for example, in the pipeline and concurrent processing systems to develop a high processing speed. The computers of this kind include IBM 3033 described in "Internal Design and Performance of IBM 3033", Nikkei Electronics, General-Purpose Computers, pp. 251-263 and IBM 360/91 discussed in "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, Jan., 1967.
The IBM 3033 processes a Branch instruction as follows to increase the processing speed. In order to start interpreting a succeeding instruction before the result of the preceding branch instruction is obtained, the system predicts whether or not the branch condition is met and interprets the succeeding instruction using the prediction until the branch instruction result is attained.
On the other hand, the IBM 360/91 is provided with a plurality of arithmetic or logical operation units (ALU's) for independently processing instructions so as to execute a high-speed processing. In this system, as soon as necessary input operands are set for an instruction, an operation of the instruction is started even if it is conceptually after another instruction, thereby implementing the concurrent processing.
According to the prior art prediction system, only the interpretation of the succeeding instruction is executed in the predicted state, namely, the operation is not effected. In the conventional concurrent processing system, it has been impossible to execute an instruction next to a branch instruction in the predicted state.
To improve the processing speed, the present invention extends the prediction processing system to be applicable to the operation of the instruction following the branch instruction. To this end, a plurality of ALU's need only be used to concurrently execute operations of a plurality of instructions; however, the inventors have found a fact that the following problem occur in this case. When a Store instruction to store data from a general-purpose register in the main storage is executed in the predicted state, if the prediction is found to be wrong after the data is stored in the cache memory or main storage, then these operations are unfavorable for the following two reasons. First, since the store instruction should have not been executed, the content of the cache memory or main storage must be recovered to the original state. Consequently, a control logic is necessary to cope with this case, and hence an excessive time loss takes place for the recovery, which may possibly prevent the system from executing a higher-speed processing. Secondly, when the cache memory or main storage is shared among a plurality of central processing units (CPU's) and channels, the wrong result of the store instruction may possibly be fetched by another CPU or channel before the pertinent CPU completes the recovery of the cache memory or main storage, which is not allowable in most cases.
The operation to execute an instruction in the predicted state for reading data from the main storage has been described in the Japanese Patent Unexamined Publication Nos. 51-40824 and 56-123041 and West German Patent Application laid-open DE-OS 3,106,881 Al (corresponding to the latter publication).